almostm4/nbtevo-system-dump
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
nbtevo-system-dump/sda3/etc/sysregs_fplane_d1.cfg
almostm4 3a0b731bad initial push
2025-06-09 15:07:26 +02:00

127 lines
12 KiB
INI
Raw Permalink Blame History

<remark> NBTevo sysregs configuration for OMAP5 </remark>
<remark> GPIO1 baseaddr 0x4AE10000, length 0x0FFF, oe 0x4AE10134, in 0x4AE10138, out 0x4AE1013C, clear 0x4AE10190, set 0x4AE10194 </remark>
<remark> GPIO2 baseaddr 0x48055000, length 0x0FFF, oe 0x48055134, in 0x48055138, out 0x4805513C, clear 0x48055190, set 0x48055194 </remark>
<remark> GPIO3 baseaddr 0x48057000, length 0x0FFF, oe 0x48057134, in 0x48057138, out 0x4805713C, clear 0x48057190, set 0x48057194 </remark>
<remark> GPIO4 baseaddr 0x48059000, length 0x0FFF, oe 0x48059134, in 0x48059138, out 0x4805913C, clear 0x48059190, set 0x48059194 </remark>
<remark> GPIO5 baseaddr 0x4805B000, length 0x0FFF, oe 0x4805B134, in 0x4805B138, out 0x4805B13C, clear 0x4805B190, set 0x4805B194 </remark>
<remark> GPIO6 baseaddr 0x4805D000, length 0x0FFF, oe 0x4805D134, in 0x4805D138, out 0x4805D13C, clear 0x4805D190, set 0x4805D194 </remark>
<remark> GPIO7 baseaddr 0x48051000, length 0x0FFF, oe 0x48051134, in 0x48051138, out 0x4805113C, clear 0x48051190, set 0x48051194 </remark>
<remark> GPIO8 baseaddr 0x48053000, length 0x0FFF, oe 0x48053134, in 0x48053138, out 0x4805313C, clear 0x48053190, set 0x48053194 </remark>
<remark> set version id to add user/group feature </remark>
<version> 200 </version>
<remark> cpurange definition: </remark>
<remark> baseaddr , length </remark>
<remark> cpudev definition: </remark>
<remark> devname , address, mode, numbits, shift, default, init, negate, accSize, visible, function , user, group, perm </remark>
<remark> emodule omap5 </remark>
<cpurange> 0x48032000, 0x0317D000 </cpurange>
<remark> Optional provision to clock USB hub "USB84604" from OMAP internal clock-signal (instead of using external crystal oscillator at hub) - not used at the moment. </remark>
<remark> usbclock </remark>
<cpudev> USB_CLOCK , 0x4AE0A310, RMW, 0x20, 0, 0x00070104, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> PINMUX , 0x4AE0C858, RMW, 0x20, 0, 0x05000500, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> Pad configuration for USB-sata-bridge </remark>
<cpudev> PINMUX_GPIO3_81 , 0x4a0028b0, RMW, 0x10, 16, 0x160e, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> Pad configuration for WLanPd </remark>
<cpudev> PINMUX_GPIO3_82 , 0x4a0028b4, RMW, 0x8, 0, 0x06, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> Pad configuration for USB[1|2]_PWR_OC </remark>
<cpudev> PINMUX_GPIO5_154 , 0x4A0029d8, RMW, 0x10, 0, 0x051e, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> PINMUX_GPIO5_153 , 0x4A0029d4, RMW, 0x10, 16, 0x051e, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> Pad configuration for USB_HUB_I2C </remark>
<cpudev> PINMUX_GPIO8_224 , 0x4A00296C, RMW, 0x10, 0, 0x0706, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> Pad configuration for USB_HUB </remark>
<cpudev> PINMUX_GPIO8_225 , 0x4A00296C, RMW, 0x10, 16, 0x0706, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> OM5 GPIO bank 1 </remark>
<cpurange> 0x4AE10000, 0x0FFF </cpurange>
<remark> GPIO1_WK15 HW_IDX4 </remark>
<cpudev> HW_IDX4_IE , 0x4AE10134, RMW, 0x01, 15, 0x01, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> HW_IDX4 , 0x4AE10138, RO, 0x01, 15, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> OM5 GPIO bank 3 </remark>
<cpurange> 0x48057000, 0x0FFF </cpurange>
<remark> GPIO3_81 USB-sata-bridge </remark>
<cpudev> USB_SATA_BRIDGE_OE , 0x48057134, RMW, 0x01, 17, 0x00, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> USB_SATA_BRIDGE , 0x4805713C, RMW, 0x01, 17, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB_SATA_BRIDGE_RST_SET , 0x48057190, WO, 0x01, 17, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB_SATA_BRIDGE_RST_CLR , 0x48057194, WO, 0x01, 17, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> GPIO3_82 WLanPd f<>r FPlane und ASIC </remark>
<cpudev> WLanPd_OE , 0x48057134, RMW, 0x01, 18, 0x00, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> WLanPd , 0x4805713C, RMW, 0x01, 18, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> WLanPd_SET , 0x48057190, WO, 0x01, 18, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> WLanPd_CLR , 0x48057194, WO, 0x01, 18, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> OM5 GPIO bank 4 </remark>
<cpurange> 0x48059000, 0x0FFF </cpurange>
<cpudev> HW_IDX1_IE , 0x48059134, RMW, 0x01, 1, 0x01, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> HW_IDX1 , 0x48059138, RO, 0x01, 1, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> HW_IDX3_IE , 0x48059134, RMW, 0x01, 3, 0x01, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> HW_IDX3 , 0x48059138, RO, 0x01, 3, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> HW_IDX0_IE , 0x48059134, RMW, 0x01, 4, 0x01, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> HW_IDX0 , 0x48059138, RO, 0x01, 4, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> OM5 GPIO bank 5 </remark>
<cpurange> 0x4805B000, 0x0FFF </cpurange>
<remark> GPIO5_153 </remark>
<cpudev> USB2_PWR_OC_IE , 0x4805B134, RMW, 0x01, 25, 0x01, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> USB2_PWR_OC , 0x4805B138, RO, 0x01, 25, 0x00, NO, YES, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> GPIO5_154 </remark>
<cpudev> USB1_PWR_OC_IE , 0x4805B134, RMW, 0x01, 26, 0x01, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> USB1_PWR_OC , 0x4805B138, RO, 0x01, 26, 0x00, NO, YES, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> WLanPd f<>r FPlane und ASIC </remark>
<remark> OM5 GPIO bank 8 </remark>
<cpurange> 0x48053000, 0x0FFF </cpurange>
<cpudev> HW_IDX2_IE , 0x48053134, RMW, 0x01, 2, 0x01, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> HW_IDX2 , 0x48053138, RO, 0x01, 2, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> WLanRst_OE , 0x48053134, RMW, 0x01, 3, 0x00, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> WLanRst , 0x4805313C, RMW, 0x01, 3, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> WLanRst_SET , 0x48053190, WO, 0x01, 3, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> WLanRst_CLR , 0x48053194, WO, 0x01, 3, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> GPIO8_224 USB HUB</remark>
<cpudev> USB_HUB_OE , 0x48053134, RMW, 0x01, 0, 0x00, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> USB_HUB , 0x4805313C, RMW, 0x01, 0, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB_HUB_RST_SET , 0x48053190, WO, 0x01, 0, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB_HUB_RST_CLR , 0x48053194, WO, 0x01, 0, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> GPIO8_225 USB HUB I2C </remark>
<cpudev> USB_HUB_I2C_OE , 0x48053134, RMW, 0x01, 1, 0x00, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> USB_HUB_I2C , 0x4805313C, RMW, 0x01, 1, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB_HUB_I2C_EN_SET , 0x48053194, WO, 0x01, 1, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB_HUB_I2C_EN_CLR , 0x48053190, WO, 0x01, 1, 0x00, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> FPGA gpio </remark>
<cpurange> 0x5e40c000, 0x00001fff </cpurange>
<cpudev> AppleAuthRst , 0x5e40c004, RMW, 1, 0, 1, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> AppleAuthRst_SET , 0x5e40c030, WO, 1, 0, 1, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> AppleAuthRst_CLR , 0x5e40c02C, WO, 1, 0, 1, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> AppleAuthRst_OE , 0x5e40c008, RMW, 1, 0, 1, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> USB2_PWR_ON , 0x5e40c004, RMW, 1, 2, 0, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB2_PWR_ON_SET , 0x5e40c02C, WO, 1, 2, 1, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB2_PWR_ON_CLR , 0x5e40c030, WO, 1, 2, 1, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB2_PWR_ON_OE , 0x5e40c008, RMW, 1, 2, 1, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> USB1_PWR_ON , 0x5e40c004, RMW, 1, 3, 0, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB1_PWR_ON_SET , 0x5e40c02C, WO, 1, 3, 1, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB1_PWR_ON_CLR , 0x5e40c030, WO, 1, 3, 1, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> USB1_PWR_ON_OE , 0x5e40c008, RMW, 1, 3, 1, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> GpsReset , 0x5e40c004, RMW, 1, 4, 1, NO, YES, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> GpsReset_SET , 0x5e40c030, WO, 1, 4, 1, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> GpsReset_CLR , 0x5e40c02C, WO, 1, 4, 1, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> GpsReset_OE , 0x5e40c008, RMW, 1, 4, 1, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpudev> NADC_PPS , 0x5e40c000, RO, 1, 5, 1, YES, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> NADC_PPS_IE , 0x5e40c008, RMW, 1, 5, 0, YES, NO, 4, NO, NULL , root, root, 0770 </cpudev>
<cpurange> 0x5e40f000, 0x00000fff </cpurange>
<cpudev> FLASH_SEL_PHYSICAL, 0x5e40f00c, RMW, 1, 0, 0, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> FLASH_SIZE_8M , 0x5e40f008, RO, 1, 22, 0, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> FLASH_NEW_LAYOUT , 0x5e40f008, RO, 1, 23, 0, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> FPGA_GOLD_LOADED , 0x5e40f008, RO, 1, 31, 0, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<cpudev> FPGA_VERSION , 0x5e40f018, RO, 32, 0, 0, NO, NO, 4, YES, NULL , root, root, 0770 </cpudev>
<remark> This is the end of the configuration </remark>
Reference in New Issue View Git Blame Copy Permalink